In recent years, silicon photonics has seen substantial technological achievements beyond early expectations. Low loss high-index contrast silicon sub-micron nanowire waveguides that can be fabricated by standard complementary metal oxide semiconductor (CMOS)-compatible processes are showing promise as realistic dense photonic integrated circuits (PICs) in various applications including optical communications, optical interconnects, signal processing and sensing. Compared with hybrid integration and freespace optical subassembly, the silicon PICs can significantly reduce the device footprint and packaging cost of optical communications modules.
In order to realize practical applications of silicon photonics device, the PIC must be packaged to couple to the optical fibers (e.g. single mode fibers) with high efficiency. This is a key challenge in the development of highly integrated silicon photonic circuits because of the large mode size mismatch between the optical fiber and high-index contrast silicon sub-micron waveguides. Even with mode size converters integrated with the silicon waveguides (invert taper is often used to enlarge the mode size of the silicon waveguide), the optical connection requires extremely accurate alignment, precise placement and robust attachment. The tight tolerance of the fiber alignment with silicon waveguide becomes a challenging issue in silicon photonics device packaging.